Creating a quality floor plan is critical for chip timing closure. Propagation delays of signals through timing paths can be dominated by the delays introduced by interconnect wiring. As line widths of new technology nodes continue to shrink, resistive characteristics of interconnect increasingly dominate signal path propagation delays, or timing. Similarly, relative distances required to connect logic are effectively increasing. Currently, the largest chips that can be efficiently manufactured are about 3 mm per side. Keeping chip size constant while reducing line widths effectively increases interconnect wire lengths. In addition, the architecture of system on a chip (SoC) designs is dominated by Intellectual Property (IP) functions that are connected using busses. The number of wires in a bus can be huge—1024 bits is not uncommon in today's designs.
Designers manually calculate propagation delay for these critical nets by using a ruler to measure distances then calculating effective resistance (e.g., wires/layer, vias required) and running trial place and route experiments to determine quality of results (QoR) of a floorplan. Manual estimations of the propagation delay may take days, with trial placement and route runs that can take weeks.